Fabrication of integrated devices, for example, and without limitation, semiconductor integrated devices, is complicated and, due to increasingly stringent requirements on device designs due to demands for greater device speed, fabrication is becoming ever more complicated. For example, integrated circuit geometries have decreased in size substantially since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed a two year/half-size rule (often called Moore's Law), which means that the number of devices on a chip doubles every two years. Today's fabrication facilities are routinely producing devices having 0.13 μm feature sizes, and tomorrow's facilities soon will be producing devices having even smaller feature sizes. In addition, integrated circuits are being layered or stacked with ever decreasing insulating thickness between each circuitry layer.
In the production of advanced integrated circuits that have minimum feature sizes of 0.13 μm and below, problems of RC delay, power consumption, and crosstalk become significant. For example, device speed is limited in part by the RC delay which is determined by the resistance of the metal used in the interconnect scheme, and the dielectric constant of the insulating dielectric material used between the metal interconnects. In addition, with decreasing geometries and device sizes, the semiconductor industry has sought to avoid parasitic capacitance and crosstalk noise caused by inadequate insulating layers in the integrated circuits. One way to achieve the desired low RC delay and higher performance in integrated circuit devices involves the use of dielectric materials in the insulating layers that have a low dielectric constant (k).
As the required value for the dielectric constant of materials is decreased due to device performance demands, there are many different types of low-k materials that are being investigated to determine whether they can perform acceptably. Most of these candidates are porous materials that can be organic materials, inorganic materials, organic compositions that might include inorganic components, and so forth.
Formation of low-k materials for use in interconnect applications has been attempted mainly by chemical vapor deposition (“CVD”) or spin-on techniques. Most such low-k materials deposited using these techniques require thermal curing after deposition to achieve desired film properties. This is problematic because there is a trend (due to the types of metals used to fabricate the integrated circuits, and to reduce thermal stress) to reduce the total thermal budget of the interconnect process flow—this includes reducing peak process temperatures as well as total process time at high process temperatures.
Process steps to reduce the dielectric constant of a material must also improve its electrical properties (such as, for example, and without limitation, by reducing failures due to early dielectric breakdowns, by enhancing its performance as an insulator, and by reducing the presence of unwanted charges within its material lattice), while maintaining or improving its physical properties. One disadvantage of using a thermal process to achieve desired film properties is that it adds an additional process step, which includes possibly an additional process tool.
The need for even further processing steps depends on several variables. For example, for porous materials there is a need to insure that mechanical and physical properties are acceptable (for example, and without limitation, stress, planarizability, and so forth).
In addition, the use of spin-on-glass materials is limited in terms of thickness by their tendency to crack when made in thick layers and cured. Spin-on-glass liquids consist of a silicon oxygen network of polymers, (typically, one of which is siloxane), dissolved in an organic solvent (typically a combination of a high boiling point solvent and a low boiling point solvent). The dissolved spin-on-glass material is coated onto a spinning semiconductor wafer or substrate. After spinning onto the wafer or substrate, low boiling point solvents are expelled using a low temperature hot plate bake process. The wafer or substrate is then heated in vacuum or nitrogen to a temperature typically in a range from about 300° C. to about 400° C. This removes higher boiling point solvents and/or organic components to create porosity in the film.
In addition to the above, a typical prior art dual damascene fabrication process begins with deposition of an oxide layer over a substrate. Next, a relatively thin silicon nitride etch stop layer is deposited over the oxide layer for use in a subsequent etching step. Next, a layer of intermetal dielectric is deposited on the etch stop layer (typically, the intermetal dielectric material is silicon oxide so that the underlying silicon nitride layer acts an effective etch stop when openings for second level interconnects are provided in the intermetal oxide layer)—the thickness of the intermetal oxide layer is chosen to be that appropriate for the second level metal wiring lines. Next, a series of photolithography steps are performed to first define a pattern of the second level wiring lines, and then to define a pattern of interconnects within the first level of the interconnect structure. Next, a mask, for example, a photoresist mask, is formed on the intermetal oxide layer where the mask includes a pattern of openings that correspond to the pattern of wiring lines desired for the second level wiring lines. Next, openings are formed in the intermetal oxide layer by etching through the openings in the photoresist mask—the etching step proceeds first through the intermetal oxide layer to leave remaining portions of the intermetal oxide layer between the openings. This first etching steps stops on the silicon nitride layer, and then etching is performed, aligned with the openings, to etch through the silicon nitride layer, leaving remaining portions of the silicon nitride layer on either side of the openings. Next, the photoresist mask is removed by ashing—it is generally necessary for the width of the openings in the patterned intermetal oxide layer to be greater than the lithography resolution limit because further photolithography steps are necessary to define the interconnects of the first level. Next, a photoresist mask is formed over the device by conventional photolithography. Next, openings are provided in the mask that expose selected portions of the first oxide layer lying within the openings. Next, etching is performed on the first oxide layer exposed within the openings in the photoresist mask to define the pattern of interconnects that make up the first level of the interconnect structure. Next, the photoresist mask is removed by ashing. Next, a layer of metal is deposited over the device to fill the openings in the intermetal oxide layer, and to fill the openings in the first oxide layer. Conventionally one overfills the openings in the intermetal oxide layer to ensure that the openings in both the intermetal oxide and the first oxide layer are completely filled. Next, excess metal is removed, typically in a CMP process, to provide the second level metal wiring lines and first level interconnects of the two level interconnect structure—the CMP step provides a planarized surface which is well suited to further processing steps.
In light of the above, there is a need for materials with improved properties for use in, among other things, improving the above-described dual damascene process. For example, there is a need for improvement in film properties such as, for example, and without limitation, one or more of: mechanical properties, thermal stability, dielectric constant, etch selectivity, resistance to isotropic strip processes, and copper diffusion barrier characteristics.